1. Field of the Invention
The present invention relates to fractional-N frequency synthesis, and more particularly to improving fractional spurious signal performance.
2. Related Art
The conventional analog integer-N PLL (phase locked loop) includes a VCO (voltage-controlled oscillator) locked to the desired output frequency Fout which is an integer multiple of a reference or phase comparison frequency Fout=N*Fcomp (where Fcomp may be derived from a reference oscillator frequency). VCO phase/frequency lock is established by a feedback control loop including a PD (phase detector, which may be implemented as a phase-frequency detector) and a feedback integer-N frequency divider—the PD compares Fcomp to the divided-down Fout/N, and provides phase/frequency control to the VCO. Thus, Fcomp determines the desired frequency resolution (also referred to as channel spacing or step size)—for each increment/decrement of N, Fout changes by Fcomp, and correspondingly the control loop will require a divide by N=Fout/Fcomp.
Frequency division is a source of phase noise (theoretically [20 log N]dB). Many applications for frequency synthesis require values of Fout and channel spacing Fcomp that require large values of N, such that the required divide-by-N control loop becomes a dominant source of phase noise.
A fractional-N PLL architecture reduces phase noise by significantly reducing the degree of frequency division required by the integer-N PLL—frequency synthesis resolution is a fractional portion of Fcomp, so that Fcomp can be greater than the channel spacing, thereby reducing the degree N of frequency division required by the control loop. For a given Fcomp and Fout, the reduction in N reduces in-band phase noise, and in addition allows increasing loop bandwidth to reduce lock time. The output frequency Fout is now Fout=(N+F)*Fcomp, where N+F comprises an integer part N and a fractional part F=Num/Den, and where Num (Numerator) and Den (Denominator) are integers.
Since digital dividers operate only with integer values, fractional division is implemented by switching between different integer divisors such that the average divisor value is equal to the loop divisor N+F. A problem with this divisor switching is that it introduces spurious sideband frequencies (“spurs” or “fractional spurs”), which must be filtered. When the offset frequency between Fout for a given channel and the primary spur is small, this spurious frequency will be less attenuated by PLL loop filter, and more sensitive to modulation nonlinearities.
Let Fos(Fch) represent the offset frequency between a given channel frequency Fch (i.e., Fout) and its primary fractional spur. For a given phase comparison frequency input to the PD Fpd (i.e. Fcomp), the offset frequency Fos(Fch) isFos(Fch,Fpd)=min(mod(Fch,Fpd),Fpd−mod(Fch,Fpd)),  (1)where the function min(x0,x1) is the smaller of x0 and x1, and
                              mod          ⁡                      (                                          F                ch                            ,                              F                pd                                      )                          =                              F            ch                    -                                    INT              ⁡                              (                                                      F                    ch                                                        F                    pd                                                  )                                      ⁢                                          F                pd                            .                                                          (        2        )            where the function INT(x) is the integer portion of any number x. Thus, when channel frequencies are closer to an integer multiple of Fpd (Fcomp), a smaller offset frequency Fos results.
These close-in primary spurs may fail to meet the spur mask requirement or be large enough to seriously degrade the RMS phase error performance. Alternatively, if the loop bandwidth is narrowed to filter out these close-in spurs, phase noise contributed by the VCO will increase, increasing integrated RMS phase error (RMS phase noise plus spurs) and phase lock time.
For example, in high data rate wireless communication applications, such as 4G/LTE and WIMAX, fractional spurs can be a significant problem both in the transmitted signal causing excessive emission power in adjacent channels, and in the receiver resulting in the down-conversion of undesired noise to baseband.